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| PI2EQX3211B 3.2Gbps 2 Differential Channel Serial Re-driver with Equalization, Squelch and Flow-Through Pinout Features * * * * * * * * * SATA s/m output drive Two 3.2Gbps differential channels Adjustable Receiver Equalization 100 Differential CML I/O's Input signal level detect and squelch for each channel Low Power (100mW per Channel) Stand-by Mode - Power Down State VCC Operating Range: 1.8V 0.1V Packaging (Pb-free & Green): -- 20-lead SSOP Description Pericom Semiconductor's PI2EQX3211B is a low power, signal re-driver. The device provides programmable equalization, by using 2 select bits, EQA and EQB, to optimize performance over a variety of physical mediums by reducing Inter-Symbol Interference. PI2EQX3211B supports two 100 Differential CML data I/O's between the Protocol ASIC to a switch fabric, across a backplane, or to extend the signals across other distant data pathways on the user's platform. The integrated equalization circuitry provides flexibility with signal integrity of the signal before the re-driver. Whereas the integrated de-emphasis circuitry provides flexibility with signal integrity of the signal after the re-driver. A low-level input signal detection and output squelch function is provided for each channel. Each channel operates fully independantly. When the channels are enabled (EN=1) and operating, that channels input signal level (on xI+/-) determines whether the output is enabled. If the input level of the channel falls below the active threshold level (Vth-) then the outputs are driven to the common mode voltage. In addition to providing signal re-conditioning, Pericom's PI2EQX3211B also provides power management Stand-by mode operated by the Enable pin. Block Diagram Pin Description Signal Detection EQA CML CML xl+ Equalizer xlEQx -Repeated 2 timesLimiting Amp xOxO+ VDD AI+ AIGND VDD BO+ BOGND EQB 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 EN VDD AO+ AOGND VDD BI+ BIGND NC EN Power Management 07-0193 1 PS8901A 08/23/07 PI2EQX3211B 3.2Gbps 2 Differential Channel Serial Re-driver Equalization, Squelch and Flow-Through Pinout Pin Description Pin # 3 4 18 Pin Name AI+ AIAO+ I/O I I O Description Positive CML Input Channel A with internal 50 pull down Negative CML Input Channel A with internal 50 pull down Positive CML Output Channel A with internal 50 pull up to VDD during normal operation and 2k when EN=0. Drives to output common mode voltage when input is AOBI+ BIBO+ O I I O 8 20 5, 9, 12, 16 1 10 2, 6, 11, 15, 19 BOEN GND EQA EQB VDD O I PWR I I PWR Equalizer Selection EQx 0 1 Compliance Channel [0:2.5dB] @ 1.6 GHz [4.5:6.5dB] @ 1.6 GHz 07-0193 2 PS8901A 08/23/07 PI2EQX3211B 3.2Gbps 2 Differential Channel Serial Re-driver Equalization, Squelch and Flow-Through Pinout Maximum Ratings (Above which useful life may be impaired. For user guidelines, not tested.) Storage Temperature........................................................ -65C to +150C Supply Voltage to Ground Potential ................................... -0.5V to +2.5V DC SIG Voltage .......................................................... -0.5V to VCC +0.5V Current Output ................................................................-25mA to +25mA Power Dissipation Continous ......................................................... 500mW Operating Temperature .............................................................. 0 to +70C Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. AC/DC Electrical Characteristics (VDD = 1.8 0.1V) Symbol Ps Parameter Supply Power Latency CML Receiver Input Differential Input Peak-toVRX-DIFFP-P peak Voltage AC Peak Common Mode VRX-CM-ACP Input Voltage VTH-SD ZRX-DIFF-DC ZRX-DC Equalization JRS JRM Residual Jitter(1,2) Random Jitter(1,2) Total Jitter Deterministic jitter 1.5 0.3 0.2 Ulp-p psrms Signal Detect Threshold DC Differential Input Impedance DC Input Impedance EN = High Conditions EN = LVCMOS Low EN = LVCMOS High From input to output Min. Typ. Max. 0.1 0.3 Units W ns 2.0 0.200 150 50 80 40 100 50 200 120 60 V mV Notes 1. K28.7 pattern is applied differentially at point A as shown in Figure 1. 2. Total jitter does not include the signal source jitter. Total jitter (TJ) = (14.1 x RJ + DJ) where RJ is random RMS jitter and DJ is maximum deterministic jitter. Signal source is a K28.5 pattern (00 1111 1010 11 0000 0101) for the deterministic jitter test and K28.7 (0011111000) or equivalent for random jitter test. Residual jitter is that which remains after equalizing media-induced losses of the environment of Figure 1 or its equivalent. The deterministic jitter at point B must be from media-induced loss, and not from clock source modulation. JItter is measured at 0V at point C of Figure 1. 07-0193 3 PS8901A 08/23/07 PI2EQX3211B 3.2Gbps 2 Differential Channel Serial Re-driver Equalization, Squelch and Flow-Through Pinout FR4 Signal Source A B Pericom PI2EQX3211B SmA Connector 30IN SmA Connector In Out C Figure 1. Test Condition Referenced in the Electrical Characteristic Table AC/DC Electrical Characteristics (TA = 0 to 70C) Symbol Parameter Conditions Min. Typ. Max. Units CML Transmitter Output (100 differential) VDIFFP VTX-DIFFP-P VTX-C (2) tF, tR ZOUT ZTX-DIFF-DC CTX Output Voltage Swing Differential Peak-to-peak Ouput Voltage Common-Mode Voltage Transition Time Output resistance DC Differential TX Impedance AC Coupling Capacitor Differential Swing | VTX-D+ - VTX-D- | VTX-DIFFP-P = 2 * | VTX-D+ - VTX-D- | | VTX-D+ + VTX-D- | / 2 20% to 80% (1) Single ended 40 80 75 50 100 200 400 VDD - 0.3 150 60 120 200 375 750 mVp-p mV V ps nF LVCMOS Control Pins VIH VIL IIH IIL Input High Voltage Input Low Voltage Input High Current Input Low Current 0.65 x VDD 0.35 x VDD 250 500 V A Note: 1. Using K28.7 (0011111000) pattern) . 2. The parameter is determined by device characterization, and is not production tested 07-0193 4 PS8901A 08/23/07 PI2EQX3211B 3.2Gbps 2 Differential Channel Serial Re-driver Equalization, Squelch and Flow-Through Pinout Packaging Mechanical: 20-lead SSOP (H20) Notes: 1. Controlling dimensions in millimeters 2. Ref.: JEDEC MS-150B/AE 3. Package Outline Exclusive of Mold Flash and Metal Burr Pericom Semiconductor Corporation 3545 N. 1st Street, San Jose, CA 95134 1-800-435-2335 * www.pericom.com Ordering Information Ordering Number PI2EQX3211BHE Package Code H Package Description Pb-Free and Green 20-lead SSOP Notes: * Thermal characteristics can be found on the company web site at www.pericom.com/packaging/ * E = Pb-free and Green * X suffix = Tape/Reel Pericom Semiconductor Corporation * 1-800-435-2336 * www.pericom.com 07-0193 5 PS8901A 08/23/07 |
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